1. Field of the Invention
This invention relates to the field of input level detection circuits, and particularly to circuits for detecting the state of a tri-state input signal.
2. Description of the Related Art
A "tri-state" signal is a digital logic signal that can assume three possible states: a logic "high" state, a logic "low" state, and a "high-impedance (hi-Z) state". In its hi-Z state, a tri-state signal presents a high impedance to the circuitry which receives it.
Tri-state signals can be beneficially employed in conventional binary logic circuits. Assume an integrated circuit (IC) has two available input/output (I/O) pins. If the pins are connected to a conventional binary receiving circuit, each I/O pin is allowed to be either a zero or a one, providing a total of four possible input combinations (00, 01, 10, 11). However, if the receiving circuit is capable of detecting the three states of a tri-state signal, a total of nine input combinations (00, 01, 0Z, 10, 11, 1Z, Z0, Z1, ZZ, where "Z"=hi-Z) are possible. Tri-state input signals thus increase the amount of information that can be conveyed into a receiving circuit for a given number of pins.
Several circuits have been developed to detect the state of an input signal that can be in one of three states. One such circuit, disclosed in U.S. Pat. No. 5,714,892 to Bowers et al., connects the incoming input signal to a window comparator, with the comparator's high and low threshold voltages established with a resistive divider. Another resistive divider is connected to pull a hi-Z input to a voltage between the low and high thresholds. The comparator outputs are fed to a NAND gate, which goes low for a hi-Z input. The comparator output is fed to a 4-transistor buffer stage along with the input signal; the outputs of the buffer stage and the comparator provide the circuit's two binary outputs.
The Bowers circuit has a number of drawbacks. Due to the large number of components needed for its implementation, it occupies a considerable amount of area on an I.C. die. As die space is expensive, the circuit's complexity incurs a high cost. Furthermore, the circuit is continuously active--i.e., its outputs continuously indicate the state of an input signal, perhaps long after the information is needed. The circuit thus draws current continuously, which can result in a shortened battery life or thermal dissipation problems, for example.
Another approach is found in U.S. Pat. No. 4,449,065 to Davies, Jr. Six transistors are arrayed to detect which of three different voltage levels an input signal is at. The input signal is connected to two of the transistors, a "pre-charge" pulse and its complement are applied to two other transistors, and an "evaluate" pulse and its complement are connected to the last two transistors. The junctions between two pairs of transistors provide the circuit's two binary outputs. The pre-charge pulse initializes the circuit, and the outputs become valid during the evaluate pulse.
The Davies circuit also suffers from a number of shortcomings. For example, the circuit requires an input signal to be within one of three distinct voltage regions to be reliably detected. As such, it is incapable of reliably detecting a hi-Z input signal, which is at an indeterminate voltage. The circuit is thus not useful in detecting tri-state input signals. The circuit also requires the generation of four timing pulses: two pre-charge pulses and two evaluate pulses. The circuitry needed to generate these pulses is not disclosed, but is likely to be complex, consuming both die space and power.